1. Field of the Invention
The present invention relates to an image reading apparatus and an image forming apparatus including the image reading apparatus.
2. Description of the Related Art
With regard to image reading apparatuses, picture element density and operating speed have been increased to cope with an increasing demand for high-quality images and high-speed operation.
Described below is one example of signal processing, from image reading by a photoelectric converter to conversion to a digital image signal, in a typical digital copier.
FIG. 1 is a block diagram illustrating an example of typical signal processing circuitry for reading signals in a typical digital copier. In this example, a clock signal from an oscillator 101 is frequency modulated by a Spread Spectrum Clock Generator (SSCG) circuit 102 and multiplied by a Phase Locked Loop (PLL) circuit 103 to produce a CCD drive signal and a signal processing IC drive signal by a timing generator 104.
The frequency modulated clock signal from the timing generator 104 drives a Charge-Coupled Device (CCD) 105, which is a photoelectric converter that converts light reflected from an original into an electrical signal. The CCD 105 outputs an analog image signal to a signal processing IC 107 via an emitter follower (EF) circuit 106. The signal processing IC 107 includes a clamping (CLMP) circuit 108, a sample-hold (SH) circuit 109, a programmable gain amplifier (PGA) 110, and an AD converter (ADC) 111.
After the analog image signal is AC coupled, the clamping circuit 108 clamps the analog image signal at an internal reference potential of the signal processing IC 107. The sample-hold circuit 109 samples the analog image signal by using a sample pulse, which is one of the signal processing IC drive signals, and maintains the level of the analog image signal to produce a continuous analog image signal. This continuous analog image signal is amplified by the programmable gain amplifier 110 and converted into digital data by the AD converter 111.
As the picture element density or image reading speed increases, the frequency of a clock signal that is not frequency modulated increases to drive the CCD 105 that reads an image and the signal processing IC 107 that processes the analog image signal output from the CCD 105. This also increases undesired electromagnetic radiation.
To avoid this problem, a unit for modulating the frequency is placed after the oscillator generating the clock frequency, or the oscillator is provided with a spread spectrum function, thereby reducing the undesired radiation strength at the frequency peak. This technology is referred to as SSCG.
FIG. 2 is a diagram illustrating an example in which SSCG is applied. The horizontal axis represents frequency and the vertical axis represents electric field strength. The SSCG circuit 102 diffuses clock frequencies having spectral characteristics of S1 to clock frequencies having spectral characteristics of S2 by frequency modulation and spectrum spreading. Accordingly, it is possible to reduce the electric field strength by an amount P and thus reduce undesired radiation, compared with the clock frequencies having the spectral characteristics of S1.
However, when a frequency modulated clock signal is used as an analog drive clock signal in the above-described example, the output offset voltage of the CCD 105 fluctuates. As a result, a problem occurs in that since the image signal level periodically fluctuates between high and low in one line when scanning the line, the levels are not the same even when the read density levels are the same. A CCD drive signal is typically generated from a highly accurate reference clock signal with an oscillation accuracy of, for example, 50 PPM, 100 PPM, etc. When the clock signal is frequency modulated to deal with undesired radiation, the frequency fluctuates with time as illustrated in the diagram in the lower part of FIG. 3, where the horizontal axis represents time and the vertical axis represents frequency. That is, the frequency smoothly fluctuates within a range of, for example, ±0.5%, ±1.0%, etc. relative to a reference frequency. Typically, this frequency modulation cycle fluctuates regularly. That is, as illustrated in the diagram in the lower part of FIG. 3, the modulation cycle is repeated such that the frequency is modulated to a short clock cycle, i.e., a high frequency (on the positive side) relative to the reference frequency, and then to a long clock cycle, i.e., a low frequency (on the negative side) with the same characteristic curve as that of the high frequency and returns to the reference frequency. The SSCG circuit 102 may randomly change the modulation cycle. Accordingly, the phase matches the reference frequency every half-cycle of the modulation.
The diagram in the upper part of FIG. 3 illustrates the fluctuation in the image level according to the modulation cycle, where the horizontal axis represents time and the vertical axis represents image level. The image level fluctuates in synchronization with the modulation cycle. When this fluctuation is repeated during scanning lines, the image level difference results in fine streaks in a read image, which are perceived as horizontal streaks. FIG. 4 is a schematic diagram illustrating a resulting image of first to sixth lines, where the horizontal axis represents main scanning direction and the vertical axis represents sub-scanning direction. This problem has not yet been resolved.